One driving method of an active matrix type display device is a dot sequential system. In a driving method for the dot sequential system, source lines are selected sequentially during a period in which one row of the scanning line is selected, and video signal is written to pixels. More specifically, switches connected to each source line are turned on sequentially by a sampling pulse generated by a source line driver circuit that has a shift register, a buffer, and the like. The sampling pulse has two levels of electric potential: “High” and “Low”.
A switch that makes a video line and the source line conduct is a switch that is turned on when the sampling pulse is “High” and is turned off when the sampling pulse is “Low”. When the sampling pulse rises and comes to be at “High” level, the switch comes to be on, and the video signal is written to the source line. Then, when the sampling pulse falls and comes to be at “Low” level, the switch comes to be off, and the electric potential of the source line is fixed. In this way, the electric potential of each source line is fixed by switches that correspond to the plurality of source lines arranged in the pixels being turned on and off in order.
The length of a period during which the sampling pulse goes from “Low” to become “High” (the period during which writing starts, the rising period) and the length of a period during which the sampling pulse goes from “High” to become “Low” (the period during which writing finishes, the falling period) depend on the characteristics (typically, on current characteristics) of a transistor that forms the buffer of the source line driver circuit and the like, but if the transistor is a thin film transistor formed of polycrystalline silicon, the length of each of these periods comes to be about 10 ns to 50 ns During the period in which the electric potential of the source line is determined, if the electric potential of the source line is changed by the effects of noise or the like, this becomes a cause of display defects such as crosstalk (ghosting) or the like. In particular, when the structure of a display device is one in which one video signal is divided up and the divided up video signals are input to the source lines via a plurality of video signal lines, because the video signals are written to a plurality of source lines simultaneously, display defects can be seen periodically and become even more prominent.
What can be considered to be one cause of the noise generated in a source line is, as shown in FIG. 20, overlapping of the rising period of the sampling pulse that selects the source line of the subsequent step. FIG. 20 is a timing chart of input signals and output signals of a conventional source line driver circuit. CK is a clock signal, SP is a start pulse, and VIDEO is a video signal input to the video signal line. The numbers 1, 2, and 3 of the video signal (VIDEO) indicate the signals that are to be written to the source lines X_1, X_2, and X_3. Reference symbols (sam_1), (sam_2), and (sam_3) are sampling pulses for sampling of three adjacent source lines, and T indicates the period during which the video signal is written to the source line. As indicated by a dotted line 80 in FIG. 20, due to overlapping of the rising period of the sampling pulse (sam_2) and the rising period of the sampling pulse (sam_3), noise is generated in the source line.
For this reason, by the sampling pulses in adjacent sampling pulses being set so that they do not overlap in terms of time, the amount of noise is reduced (Refer to Patent Document 1 and Patent Document 2). Furthermore, as shown in FIG. 21, a method is used in which the width of the sampling pulse is made shorter than a half-cycle of the clock signal by a pulse width controller (PWC) or the like. By this method, the writing period T is made to be shorter than the writing period T shown in FIG. 20.
Patent Document 1: Japanese Published Patent Application No. 2001-265289
Patent Document 2: Japanese Published Patent Application No. 2003-337320